// 输入[15:0]data_in中，从低位开始找到第一个1出现的位置。
module top(
           input clk,
           input rst_n,
           input [15: 0] data_in,
           input data_in_valid,
           output reg [3: 0] position
       );

wire [15: 0] data_in_r;
assign data_in_r = ~(data_in - 1) & data_in;

always@(posedge clk or negedge rst_n)
	begin
		if (!rst_n)
			position <= 0;
		else
			begin
				case (data_in_r)
					16'd1:
						position <= 4'd0;
					16'b0000000000000010:
						position <= 4'd1;
					16'b0000000000000100:
						position <= 4'd2;
					16'b0000000000001000:
						position <= 4'd3;
					16'b0000000000010000:
						position <= 4'd4;
					16'b0000000000100000:
						position <= 4'd5;
					16'b0000000001000000:
						position <= 4'd6;
					16'b0000000010000000:
						position <= 4'd7;
					16'b0000000100000000:
						position <= 4'd8;
					16'b0000001000000000:
						position <= 4'd9;
					16'b0000010000000000:
						position <= 4'd10;
					16'b0000100000000000:
						position <= 4'd11;
					16'b0001000000000000:
						position <= 4'd12;
					16'b0010000000000000:
						position <= 4'd13;
					16'b0100000000000000:
						position <= 4'd14;
					16'b1000000000000000:
						position <= 4'd15;
					default:
						position <= 0;
				endcase
			end
	end

endmodule
